19template <
unsigned Id,
typename TCpuAccessor,
typename TEndianessC>
class MemRwOptional {
21 static constexpr bool kReadOnly =
false;
26 explicit MemRwOptional(u8 *
const buf,
const me_size_t buf_size,
const me_adr_t vadr_offset)
27 : buf_(buf), vadr_offset_(vadr_offset), buf_size_(buf_size) {}
58 template <
typename T>
ReadResult<T> Read(TCpuAccessor &cpua, me_adr_t vadr)
const {
61 std::is_same<T, u32>::value ||
62 std::is_same<T, u16>::value ||
63 std::is_same<T, u8>::value,
64 "Read only allows u32, u16 and u8");
66 static_cast<void>(cpua);
68 assert(buf_ !=
nullptr && buf_size_ != 0U);
70 const me_adr_t padr = ConvertToPhysicalAdr(vadr);
71 assert(IsPAdrInRange(padr) ==
true);
72 T val = *
reinterpret_cast<const T *
>(&buf_[padr]);
73 T cval = TEndianessC::template Convert<T>(val);
78 template <
typename T>
WriteResult<T> Write(TCpuAccessor &cpua, me_adr_t vadr, T value)
const {
81 std::is_same<T, u32>::value ||
82 std::is_same<T, u16>::value ||
83 std::is_same<T, u8>::value,
84 "Write only allows u32, u16 and u8 types");
86 static_cast<void>(cpua);
88 assert(buf_ !=
nullptr && buf_size_ != 0U);
89 const me_adr_t padr = ConvertToPhysicalAdr(vadr);
90 assert(IsPAdrInRange(padr) ==
true);
92 *
reinterpret_cast<T *const
>(&buf_[padr]) = value;
97 bool IsVAdrInRange(me_adr_t vadr)
const {
99 if (buf_ ==
nullptr || buf_size_ == 0U) {
103 const me_adr_t padr = ConvertToPhysicalAdr(vadr);
104 if (IsPAdrInRange(padr) ==
false) {
111 u8 *
const buf_{
nullptr};
112 const me_adr_t vadr_offset_{0U};
113 const me_size_t buf_size_{0U};
115 me_adr_t ConvertToPhysicalAdr(me_adr_t vadr)
const {
return vadr - vadr_offset_; }
116 bool IsPAdrInRange(me_adr_t padr)
const {
return padr < buf_size_; }