ternary_instr_with_shift.h

#pragma once
#include "libmicroemu/internal/decoder/decoder.h"
#include "libmicroemu/internal/executor/instr/post_exec.h"
#include "libmicroemu/internal/executor/instr_context.h"
#include "libmicroemu/internal/executor/instr_exec_results.h"
#include "libmicroemu/internal/result.h"
#include "libmicroemu/internal/utils/rarg.h"
#include "libmicroemu/register_details.h"
#include "libmicroemu/types.h"
 
namespace libmicroemu::internal {

template <typename TInstrContext> class Eor2ShiftOp {
public:
  template <typename TDest, typename TArg0, typename TArg1>
  static Result<InstrExecFlagsSet> Call(TInstrContext &ictx, const InstrFlagsSet &iflags,
                                        const TDest &rd, const TArg0 &rn, const TArg1 &rm,
                                        const ImmShiftResults &shift_res) {
    auto n = ictx.cpua.ReadRegister(rn.Get());
    auto m = ictx.cpua.ReadRegister(rm.Get());
    auto apsr = ictx.cpua.template ReadSpecialRegister<SpecialRegisterId::kApsr>();
    const auto shift_val = Alu32::Shift_C(m, shift_res.type, shift_res.value,
                                          (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
    const auto &shifted = shift_val.result;
 
    const u32 result = Alu32::EOR(n, shifted);
    const auto op_res =
        OpResult{result, shift_val.carry_out, (apsr & ApsrRegister::kVMsk) == ApsrRegister::kVMsk};
 
    PostExecWriteRegPcExcluded::Call(ictx, rd, op_res.value);
    PostExecOptionalSetFlags::Call(ictx, iflags, op_res);
    PostExecAdvancePcAndIt::Call(ictx, iflags);
    return Ok(kNoInstrExecFlags);
  }
};

template <typename TInstrContext> class Orr2ShiftOp {
public:
  template <typename TDest, typename TArg0, typename TArg1>
  static Result<InstrExecFlagsSet> Call(TInstrContext &ictx, const InstrFlagsSet &iflags,
                                        const TDest &rd, const TArg0 &rn, const TArg1 &rm,
                                        const ImmShiftResults &shift_res) {
    auto n = ictx.cpua.ReadRegister(rn.Get());
    auto m = ictx.cpua.ReadRegister(rm.Get());
    auto apsr = ictx.cpua.template ReadSpecialRegister<SpecialRegisterId::kApsr>();
    const auto shift_val = Alu32::Shift_C(m, shift_res.type, shift_res.value,
                                          (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
    const auto &shifted = shift_val.result;
 
    const u32 result = Alu32::OR(n, shifted);
    const auto op_res =
        OpResult{result, shift_val.carry_out, (apsr & ApsrRegister::kVMsk) == ApsrRegister::kVMsk};
    PostExecWriteRegPcExcluded::Call(ictx, rd, op_res.value);
    PostExecOptionalSetFlags::Call(ictx, iflags, op_res);
    PostExecAdvancePcAndIt::Call(ictx, iflags);
    return Ok(kNoInstrExecFlags);
  }
};

template <typename TInstrContext> class And2ShiftOp {
public:
  template <typename TDest, typename TArg0, typename TArg1>
  static Result<InstrExecFlagsSet> Call(TInstrContext &ictx, const InstrFlagsSet &iflags,
                                        const TDest &rd, const TArg0 &rn, const TArg1 &rm,
                                        const ImmShiftResults &shift_res) {
    auto n = ictx.cpua.ReadRegister(rn.Get());
    auto m = ictx.cpua.ReadRegister(rm.Get());
    auto apsr = ictx.cpua.template ReadSpecialRegister<SpecialRegisterId::kApsr>();
    const auto shift_val = Alu32::Shift_C(m, shift_res.type, shift_res.value,
                                          (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
    const auto &shifted = shift_val.result;
 
    const u32 result = Alu32::AND(n, shifted);
    const auto op_res =
        OpResult{result, shift_val.carry_out, (apsr & ApsrRegister::kVMsk) == ApsrRegister::kVMsk};
    PostExecWriteRegPcExcluded::Call(ictx, rd, op_res.value);
    PostExecOptionalSetFlags::Call(ictx, iflags, op_res);
    PostExecAdvancePcAndIt::Call(ictx, iflags);
    return Ok(kNoInstrExecFlags);
  }
};

template <typename TInstrContext> class Bic2ShiftOp {
public:
  template <typename TDest, typename TArg0, typename TArg1>
  static Result<InstrExecFlagsSet> Call(TInstrContext &ictx, const InstrFlagsSet &iflags,
                                        const TDest &rd, const TArg0 &rn, const TArg1 &rm,
                                        const ImmShiftResults &shift_res) {
    auto n = ictx.cpua.ReadRegister(rn.Get());
    auto m = ictx.cpua.ReadRegister(rm.Get());
    auto apsr = ictx.cpua.template ReadSpecialRegister<SpecialRegisterId::kApsr>();
    const auto shift_val = Alu32::Shift_C(m, shift_res.type, shift_res.value,
                                          (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
    const auto &shifted = shift_val.result;
 
    const u32 result = Alu32::AND(n, ~shifted);
    const auto op_res =
        OpResult{result, shift_val.carry_out, (apsr & ApsrRegister::kVMsk) == ApsrRegister::kVMsk};
    PostExecWriteRegPcExcluded::Call(ictx, rd, op_res.value);
    PostExecOptionalSetFlags::Call(ictx, iflags, op_res);
    PostExecAdvancePcAndIt::Call(ictx, iflags);
    return Ok(kNoInstrExecFlags);
  }
};

template <typename TInstrContext> class Sbc2ShiftOp {
public:
  template <typename TDest, typename TArg0, typename TArg1>
  static Result<InstrExecFlagsSet> Call(TInstrContext &ictx, const InstrFlagsSet &iflags,
                                        const TDest &rd, const TArg0 &rn, const TArg1 &rm,
                                        const ImmShiftResults &shift_res) {
    auto n = ictx.cpua.ReadRegister(rn.Get());
    auto m = ictx.cpua.ReadRegister(rm.Get());
    auto apsr = ictx.cpua.template ReadSpecialRegister<SpecialRegisterId::kApsr>();
    const auto shifted = Alu32::Shift(m, shift_res.type, shift_res.value,
                                      (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
    const auto result =
        Alu32::AddWithCarry(n, ~shifted, (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
 
    const auto op_res = OpResult{result.value, result.carry_out, result.overflow};
    PostExecWriteRegPcExcluded::Call(ictx, rd, op_res.value);
    PostExecOptionalSetFlags::Call(ictx, iflags, op_res);
    PostExecAdvancePcAndIt::Call(ictx, iflags);
    return Ok(kNoInstrExecFlags);
  }
};

template <typename TInstrContext> class Sub2ShiftOp {
public:
  template <typename TDest, typename TArg0, typename TArg1>
  static Result<InstrExecFlagsSet> Call(TInstrContext &ictx, const InstrFlagsSet &iflags,
                                        const TDest &rd, const TArg0 &rn, const TArg1 &rm,
                                        const ImmShiftResults &shift_res) {
    auto n = ictx.cpua.ReadRegister(rn.Get());
    auto m = ictx.cpua.ReadRegister(rm.Get());
    auto apsr = ictx.cpua.template ReadSpecialRegister<SpecialRegisterId::kApsr>();
    const auto shifted = Alu32::Shift(m, shift_res.type, shift_res.value,
                                      (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
    const auto result = Alu32::AddWithCarry(n, ~shifted, true);
    const auto op_res = OpResult{result.value, result.carry_out, result.overflow};
    PostExecWriteRegPcExcluded::Call(ictx, rd, op_res.value);
    PostExecOptionalSetFlags::Call(ictx, iflags, op_res);
    PostExecAdvancePcAndIt::Call(ictx, iflags);
    return Ok(kNoInstrExecFlags);
  }
};

template <typename TInstrContext> class Rsb2ShiftOp {
public:
  template <typename TDest, typename TArg0, typename TArg1>
  static Result<InstrExecFlagsSet> Call(TInstrContext &ictx, const InstrFlagsSet &iflags,
                                        const TDest &rd, const TArg0 &rn, const TArg1 &rm,
                                        const ImmShiftResults &shift_res) {
    auto n = ictx.cpua.ReadRegister(rn.Get());
    auto m = ictx.cpua.ReadRegister(rm.Get());
    auto apsr = ictx.cpua.template ReadSpecialRegister<SpecialRegisterId::kApsr>();
    const auto shifted = Alu32::Shift(m, shift_res.type, shift_res.value,
                                      (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
    const auto result = Alu32::AddWithCarry(~n, shifted, true);
    const auto op_res = OpResult{result.value, result.carry_out, result.overflow};
    PostExecWriteRegPcExcluded::Call(ictx, rd, op_res.value);
    PostExecOptionalSetFlags::Call(ictx, iflags, op_res);
    PostExecAdvancePcAndIt::Call(ictx, iflags);
    return Ok(kNoInstrExecFlags);
  }
};

template <typename TInstrContext> class Add2ShiftOp {
public:
  template <typename TDest, typename TArg0, typename TArg1>
  static Result<InstrExecFlagsSet> Call(TInstrContext &ictx, const InstrFlagsSet &iflags,
                                        const TDest &rd, const TArg0 &rn, const TArg1 &rm,
                                        const ImmShiftResults &shift_res) {
    auto n = ictx.cpua.ReadRegister(rn.Get());
    auto m = ictx.cpua.ReadRegister(rm.Get());
    auto apsr = ictx.cpua.template ReadSpecialRegister<SpecialRegisterId::kApsr>();
    const auto shifted = Alu32::Shift(m, shift_res.type, shift_res.value,
                                      (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
    const auto result = Alu32::AddWithCarry(n, shifted, false);
    const auto op_res = OpResult{result.value, result.carry_out, result.overflow};
    PostExecWriteRegPcExcluded::Call(ictx, rd, op_res.value);
    PostExecOptionalSetFlags::Call(ictx, iflags, op_res);
    PostExecAdvancePcAndIt::Call(ictx, iflags);
    return Ok(kNoInstrExecFlags);
  }
};

template <typename TInstrContext> class Adc2ShiftOp {
public:
  template <typename TDest, typename TArg0, typename TArg1>
  static Result<InstrExecFlagsSet> Call(TInstrContext &ictx, const InstrFlagsSet &iflags,
                                        const TDest &rd, const TArg0 &rn, const TArg1 &rm,
                                        const ImmShiftResults &shift_res) {
    auto n = ictx.cpua.ReadRegister(rn.Get());
    auto m = ictx.cpua.ReadRegister(rm.Get());
    auto apsr = ictx.cpua.template ReadSpecialRegister<SpecialRegisterId::kApsr>();
    const auto shifted = Alu32::Shift(m, shift_res.type, shift_res.value,
                                      (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
    const auto result =
        Alu32::AddWithCarry(n, shifted, (apsr & ApsrRegister::kCMsk) == ApsrRegister::kCMsk);
    const auto op_res = OpResult{result.value, result.carry_out, result.overflow};
    PostExecWriteRegPcExcluded::Call(ictx, rd, op_res.value);
    PostExecOptionalSetFlags::Call(ictx, iflags, op_res);
    PostExecAdvancePcAndIt::Call(ictx, iflags);
    return Ok(kNoInstrExecFlags);
  }
};
 
template <typename TOp, typename TInstrContext> class TernaryInstrWithShift {
public:
  using It = typename TInstrContext::It;
  using Pc = typename TInstrContext::Pc;
 
  template <typename TDest, typename TArg0, typename TArg1>
  static Result<InstrExecResult> Call(TInstrContext &ictx, const InstrFlagsSet &iflags,
                                      const TDest &rd, const TArg0 &rn, const TArg1 &rm,
                                      const ImmShiftResults &shift_res) {
    TRY_ASSIGN(condition_passed, InstrExecResult, It::ConditionPassed(ictx.cpua));
    if (!condition_passed) {
      PostExecAdvancePcAndIt::Call(ictx, iflags);
      return Ok(InstrExecResult{kNoInstrExecFlags});
    }
 
    TRY_ASSIGN(eflags, InstrExecResult, TOp::Call(ictx, iflags, rd, rn, rm, shift_res));
 
    return Ok(InstrExecResult{eflags});
  }
 
private:
  TernaryInstrWithShift() = delete;

  ~TernaryInstrWithShift() = delete;

  TernaryInstrWithShift(const TernaryInstrWithShift &r_src) = delete;

  TernaryInstrWithShift &operator=(const TernaryInstrWithShift &r_src) = delete;

  TernaryInstrWithShift(TernaryInstrWithShift &&r_src) = delete;

  TernaryInstrWithShift &operator=(TernaryInstrWithShift &&r_src) = delete;
};
 
} // namespace libmicroemu::internal