libmicroemu 0.2.0
ARM Microcontroller Emulator Library
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register_details.h
1#pragma once
2
3#include "libmicroemu/types.h"
4
5namespace libmicroemu {
6
7template <unsigned last_bit, unsigned first_bit> static constexpr u32 BitMask() {
8 if constexpr (last_bit == sizeof(u32) * 8U - 1U) {
9 return ~0U << first_bit;
10 } else {
11 return ((1U << (last_bit - first_bit + 1U)) - 1U) << first_bit;
12 }
13}
14
15struct RegisterOffsets {
16 static constexpr u8 kBusFaultOffset = 8U;
17 static constexpr u8 kUsageFaultOffset = 16U;
18};
19
20struct CfsrUsageFault {
21 // Bit positions for the UsageFault in the CFSR register
22 static constexpr u8 kBit15Pos = 31U;
23 static constexpr u8 kBit0Pos = 16U;
24 static constexpr u32 kMsk = BitMask<kBit15Pos, kBit0Pos>();
25
26 // UFSR flag for DIVBYZERO (bit 9 + offset)
27 static constexpr u8 kDivByZeroBitPos = 9U + RegisterOffsets::kUsageFaultOffset;
28 static constexpr u32 kDivByZeroMsk = 1U << kDivByZeroBitPos;
29
30 // UFSR flag for UNALIGNED (bit 8 + offset)
31 static constexpr u8 kUnalignedBitPos = 8U + RegisterOffsets::kUsageFaultOffset;
32 static constexpr u32 kUnalignedMsk = 1U << kUnalignedBitPos;
33
34 // UFSR flag for NOCP (bit 3 + offset)
35 static constexpr u8 kNoCpBitPos = 3U + RegisterOffsets::kUsageFaultOffset;
36 static constexpr u32 kNoCpMsk = 1U << kNoCpBitPos;
37
38 // UFSR flag for INVPC (bit 2 + offset)
39 static constexpr u8 kInvPcBitPos = 2U + RegisterOffsets::kUsageFaultOffset;
40 static constexpr u32 kInvPcMsk = 1U << kInvPcBitPos;
41
42 // UFSR flag for INVSTATE (bit 1 + offset)
43 static constexpr u8 kInvStateBitPos = 1U + RegisterOffsets::kUsageFaultOffset;
44 static constexpr u32 kInvStateMsk = 1U << kInvStateBitPos;
45
46 // UFSR flag for UNDEFINSTR (bit 0 + offset)
47 static constexpr u8 kUndefInstrBitPos = 0U + RegisterOffsets::kUsageFaultOffset;
48 static constexpr u32 kUndefInstrMsk = 1U << kUndefInstrBitPos;
49};
50
51struct CfsrBusFault {
52 // Bit positions for the BusFault in the CFSR register
53 static constexpr u8 kBit7Pos = 15U;
54 static constexpr u8 kBit0Pos = 8U;
55 static constexpr u32 kMsk = BitMask<kBit7Pos, kBit0Pos>();
56
57 // BFSR flag for BFARVALID (bit 7 + offset)
58 static constexpr u8 kBfarValidBitPos = 7U + RegisterOffsets::kBusFaultOffset;
59 static constexpr u32 kBfarValidMsk = 1U << kBfarValidBitPos;
60
61 // BFSR flag for LSPERR (bit 5 + offset)
62 static constexpr u8 kLsperrBitPos = 5U + RegisterOffsets::kBusFaultOffset;
63 static constexpr u32 kLsperrMsk = 1U << kLsperrBitPos;
64
65 // BFSR flag for STKERR (bit 4 + offset)
66 static constexpr u8 kStkerrBitPos = 4U + RegisterOffsets::kBusFaultOffset;
67 static constexpr u32 kStkerrMsk = 1U << kStkerrBitPos;
68
69 // BFSR flag for UNSTKERR (bit 3 + offset)
70 static constexpr u8 kUnstkerrBitPos = 3U + RegisterOffsets::kBusFaultOffset;
71 static constexpr u32 kUnstkerrMsk = 1U << kUnstkerrBitPos;
72
73 // BFSR flag for IMPRECISERR (bit 2 + offset)
74 static constexpr u8 kImpreciseErrBitPos = 2U + RegisterOffsets::kBusFaultOffset;
75 static constexpr u32 kImpreciseErrMsk = 1U << kImpreciseErrBitPos;
76
77 // BFSR flag for PRECISERR (bit 1 + offset)
78 static constexpr u8 kPreciseErrBitPos = 1U + RegisterOffsets::kBusFaultOffset;
79 static constexpr u32 kPreciseErrMsk = 1U << kPreciseErrBitPos;
80
81 // BFSR flag for IBUSERR (bit 0 + offset)
82 static constexpr u8 kIbuErrBitPos = 0U + RegisterOffsets::kBusFaultOffset;
83 static constexpr u32 kIbuErrMsk = 1U << kIbuErrBitPos;
84};
85
86struct CfsrMemManage {
87 // Bit positions for the MemManage in the CFSR register
88 static constexpr u8 kBit7Pos = 7U;
89 static constexpr u8 kBit0Pos = 0U;
90 static constexpr u32 kMsk = BitMask<kBit7Pos, kBit0Pos>();
91
92 // MMFSR flag for MMARVALID (bit 7)
93 static constexpr u8 kMmarValidBitPos = 7U;
94 static constexpr u32 kMmarValidMsk = 1U << kMmarValidBitPos;
95
96 // MMFSR flag for LSPERR (bit 5)
97 static constexpr u8 kLsperrBitPos = 5U;
98 static constexpr u32 kLsperrMsk = 1U << kLsperrBitPos;
99
100 // MMFSR flag for STKERR (bit 4)
101 static constexpr u8 kStkerrBitPos = 4U;
102 static constexpr u32 kStkerrMsk = 1U << kStkerrBitPos;
103
104 // MMFSR flag for UNSTKERR (bit 3)
105 static constexpr u8 kUnstkerrBitPos = 3U;
106 static constexpr u32 kUnstkerrMsk = 1U << kUnstkerrBitPos;
107
108 // MMFSR flag for DACCVIOL (bit 1)
109 static constexpr u8 kDaccViolBitPos = 1U;
110 static constexpr u32 kDaccViolMsk = 1U << kDaccViolBitPos;
111
112 // MMFSR flag for IACCVIOL (bit 0)
113 static constexpr u8 kIaccViolBitPos = 0U;
114 static constexpr u32 kIaccViolMsk = 1U << kIaccViolBitPos;
115};
116
117struct SysTickRegister {
118 // SysTick Control and Status Register (CSR) flags
119 static constexpr u8 kCsrEnablePos = 0U;
120 static constexpr u32 kCsrEnableMsk = 1U << kCsrEnablePos;
121
122 static constexpr u8 kCsrTickIntPos = 1U;
123 static constexpr u32 kCsrTickIntMsk = 1U << kCsrTickIntPos;
124
125 static constexpr u8 kCsrClockSourcePos = 2U;
126 static constexpr u32 kCsrClockSourceMsk = 1U << kCsrClockSourcePos;
127
128 static constexpr u8 kCsrCountFlagPos = 16U;
129 static constexpr u32 kCsrCountFlagMsk = 1U << kCsrCountFlagPos;
130
131 // SysTick Reload Value Register (RVR)
132 static constexpr u8 kRvrReloadPos = 0U;
133 static constexpr u32 kRvrReloadMsk = 0x00FFFFFFU << kRvrReloadPos; // 24-bit reload value
134
135 // SysTick Current Value Register (CVR)
136 static constexpr u8 kCvrCurrentPos = 0U;
137 static constexpr u32 kCvrCurrentMsk = 0x00FFFFFFU << kCvrCurrentPos; // 24-bit current value
138
139 // SysTick Calibration Value Register (CALIB)
140 static constexpr u8 kCalibNoRefPos = 31U;
141 static constexpr u32 kCalibNoRefMsk = 1U << kCalibNoRefPos;
142
143 static constexpr u8 kCalibSkewPos = 30U;
144 static constexpr u32 kCalibSkewMsk = 1U << kCalibSkewPos;
145
146 static constexpr u8 kCalibTenMsPos = 0U;
147 static constexpr u32 kCalibTenMsMsk = 0x00FFFFFFU << kCalibTenMsPos; // 24-bit tenms value
148};
149
150struct CcrRegister {
151 // CCR - Configuration and Control Register flags
152 static constexpr u8 kStkAlignPos = 9U; // Stack alignment bit
153 static constexpr u32 kStkAlignMsk = 1U << kStkAlignPos; // Stack alignment bit mask
154
155 static constexpr u8 kNonBaseThreadEnablePos = 0U; // Non-base thread enable bit
156 static constexpr u32 kNonBaseThreadEnableMsk =
157 1U << kNonBaseThreadEnablePos; // Non-base thread enable mask
158
159 static constexpr u8 kUserSettablePendSvPos = 1U; // User-settable PendSV bit
160 static constexpr u32 kUserSettablePendSvMsk =
161 1U << kUserSettablePendSvPos; // User-settable PendSV mask
162
163 static constexpr u8 kUnalignTrapEnablePos = 3U; // Unaligned access trap enable bit
164 static constexpr u32 kUnalignTrapEnableMsk =
165 1U << kUnalignTrapEnablePos; // Unaligned access trap enable mask
166
167 static constexpr u8 kDivByZeroTrapEnablePos = 4U; // Divide by zero trap enable bit
168 static constexpr u32 kDivByZeroTrapEnableMsk =
169 1U << kDivByZeroTrapEnablePos; // Divide by zero trap enable mask
170
171 static constexpr u8 kMainStackAlignPos = 9U; // Main stack alignment bit
172 static constexpr u32 kMainStackAlignMsk = 1U << kMainStackAlignPos; // Main stack alignment mask
173
174 static constexpr u8 kIgnoreLsbOnDataPos = 10U; // Ignore LSB in data address comparisons bit
175 static constexpr u32 kIgnoreLsbOnDataMsk =
176 1U << kIgnoreLsbOnDataPos; // Ignore LSB in data address mask
177
178 static constexpr u8 kBranchPredictionEnablePos = 18U; // Branch prediction enable bit
179 static constexpr u32 kBranchPredictionEnableMsk =
180 1U << kBranchPredictionEnablePos; // Branch prediction enable mask
181
182 static constexpr u8 kL1CacheEnablePos = 19U; // L1 cache enable bit
183 static constexpr u32 kL1CacheEnableMsk = 1U << kL1CacheEnablePos; // L1 cache enable mask
184};
185
186struct ApsrRegister {
187 // APSR - Application Program Status Register flags
188 static constexpr u8 kNPos = 31U; // Negative condition flag
189 static constexpr u8 kZPos = 30U; // Zero condition flag
190 static constexpr u8 kCPos = 29U; // Carry condition flag
191 static constexpr u8 kVPos = 28U; // Overflow condition flag
192 static constexpr u8 kQPos = 27U; // Saturation condition flag
193 static constexpr u8 kGeBit0 = 16U; // Bit 0 of greater than or Equal flags
194 static constexpr u8 kGeBit3 = 19U; // Bit 3 of greater than or Equal flags
195
196 // APSR masks
197 static constexpr u32 kNMsk = 1U << kNPos; // Negative condition flag mask
198 static constexpr u32 kZMsk = 1U << kZPos; // Zero condition flag mask
199 static constexpr u32 kCMsk = 1U << kCPos; // Carry condition flag mask
200 static constexpr u32 kVMsk = 1U << kVPos; // Overflow condition flag mask
201 static constexpr u32 kQMsk = 1U << kQPos; // Saturation condition flag mask
202
203 // Greater than or Equal (GE) flags mask (bits 19 to 16)
204 static constexpr u32 kGeMsk = BitMask<kGeBit3, kGeBit0>();
205};
206
207struct EpsrRegister {
208 // EPSR bit positions
209 static constexpr u8 kItBit1Pos = 26U;
210 static constexpr u8 kItBit0Pos = 25U;
211 static constexpr u8 kTPos = 24U; // Thumb mode bit
212 static constexpr u8 kItBit7Pos = 15U;
213 static constexpr u8 kItBit2Pos = 10U;
214
215 // EPSR masks
216 static constexpr u32 kTMsk = 1U << kTPos; // Thumb mode bit mask
217 static constexpr u32 kItBit1to0Msk = BitMask<kItBit1Pos, kItBit0Pos>(); // IT bits 1-0
218 static constexpr u32 kItBit7to2Msk = BitMask<kItBit7Pos, kItBit2Pos>(); // IT bits 7-2
219 static constexpr u32 kItMsk = kItBit1to0Msk | kItBit7to2Msk; // Full IT bits mask
220};
221
222struct IstateRegister {
223 // Istate bit positions
224 static constexpr u8 kItBit7Pos = 7U;
225 static constexpr u8 kItBit4Pos = 4U;
226 static constexpr u8 kItBit3Pos = 3U;
227 static constexpr u8 kItBit2Pos = 2U;
228 static constexpr u8 kItBit1Pos = 1U;
229 static constexpr u8 kItBit0Pos = 0U;
230
231 // Istate masks for specific bit ranges
232 static constexpr u32 kItBit1to0Msk = BitMask<kItBit1Pos, kItBit0Pos>();
233 static constexpr u32 kItBit2to0Msk = BitMask<kItBit2Pos, kItBit0Pos>();
234 static constexpr u32 kItBit3to0Msk = BitMask<kItBit3Pos, kItBit0Pos>();
235 static constexpr u32 kItBit3to1Msk = BitMask<kItBit3Pos, kItBit1Pos>();
236 static constexpr u32 kItBit4to0Msk = BitMask<kItBit4Pos, kItBit0Pos>();
237 static constexpr u32 kItBit7to2Msk = BitMask<kItBit7Pos, kItBit2Pos>();
238 static constexpr u32 kItBit7to4Msk = BitMask<kItBit7Pos, kItBit4Pos>();
239
240 // Full Istate mask (bits 7 to 0)
241 static constexpr u32 kItMsk = BitMask<kItBit7Pos, kItBit0Pos>();
242};
243
244struct IpsrRegister {
245 // IPSR bit positions
246 static constexpr u8 kExceptionNumberBit0Pos = 0U;
247 static constexpr u8 kExceptionNumberBit8Pos = 8U;
248
249 // IPSR masks
250 static constexpr u32 kExceptionNumberMsk =
251 BitMask<kExceptionNumberBit8Pos, kExceptionNumberBit0Pos>(); // Exception number mask
252};
253
254struct SysCtrlRegister {
255 // SYSCTRL bit positions
256 static constexpr u8 kTPos = 0U; // Thumb mode bit
257 static constexpr u8 kExecModePos = 1U; // Execution mode bit
258 static constexpr u8 kControlNPrivPos = 2U; // Control register nPRIV bit
259 static constexpr u8 kControlSpSelPos = 3U; // Control register SPSEL bit
260 static constexpr u8 kControlFpcaPos = 4U; // Processor includes FP extension bit
261
262 // SYSCTRL masks
263 static constexpr u32 kTMsk = 1U << kTPos; // Thumb mode bit mask
264 static constexpr u32 kExecModeMsk = 1U << kExecModePos; // Execution mode bit mask
265 static constexpr u32 kExecModeThread = 0U << kExecModePos; // Execution mode thread
266 static constexpr u32 kExecModeHandler = 1U << kExecModePos; // Execution mode handler
267
268 static constexpr u32 kControlSpSelMsk = 1U << kControlSpSelPos; // Control register SPSEL bit mask
269 static constexpr u32 kControlNPrivMsk = 1U << kControlNPrivPos; // Control register nPRIV bit mask
270 static constexpr u32 kControlFpcaMsk = 1U << kControlFpcaPos; // uC includes FP extension bit mask
271};
272
273struct ControlRegister {
274 // Control bit positions
275 static constexpr u8 kNPrivPos = 0U; // Privilige mode bit
276 static constexpr u8 kSpselPos = 1U; // Spsel bit
277 static constexpr u8 kFpcaPos = 2U; // Processor includes FP extension bit
278
279 // Control masks
280 static constexpr u32 kNPrivMsk = 1U << kNPrivPos;
281 static constexpr u32 kSpselMsk = 1U << kSpselPos;
282 static constexpr u32 kFpcaMsk = 1U << kFpcaPos;
283
284 // Control masks for specific bit ranges
285 static constexpr u32 kControlBit1toBit0Msk = BitMask<kSpselPos, kNPrivPos>();
286 static constexpr u32 kControlBit2toBit0Msk = BitMask<kFpcaPos, kNPrivPos>();
287};
288
289} // namespace libmicroemu
libmicroemu
The libmicroemu namespace contains all classes and functions of the libmicroemu which are public.
Definition bkpt_flags.h:6
libmicroemu::ApsrRegister
Definition register_details.h:186
libmicroemu::CcrRegister
Definition register_details.h:150
libmicroemu::CfsrBusFault
Definition register_details.h:51
libmicroemu::CfsrMemManage
Definition register_details.h:86
libmicroemu::CfsrUsageFault
Definition register_details.h:20
libmicroemu::ControlRegister
Definition register_details.h:273
libmicroemu::EpsrRegister
Definition register_details.h:207
libmicroemu::IpsrRegister
Definition register_details.h:244
libmicroemu::IstateRegister
Definition register_details.h:222
libmicroemu::RegisterOffsets
Definition register_details.h:15
libmicroemu::SysCtrlRegister
Definition register_details.h:254
libmicroemu::SysTickRegister
Definition register_details.h:117
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